module WB(
    // control signals    
    input JALFlush_from_MEM_WB,                            // work at WB  
    input RegWrite_from_MEM_WB, MeMtoReg_from_MEM_WB,          // work at WB
    
    // data
    input [31:0] JalAddr_from_MEM_WB,                 // work at WB    
    input [31:0] pc8_from_MEM_WB,                     // work at WB    
    input [4:0]  rd_from_MEM_WB,                      // work at WB
    input [31:0] Res_from_MEM_WB,                     // work at WB
    input  overflow_from_MEM_WB,                      // work at WB
    input [31:0] Data_from_MEM_WB,                 // work at WB

    output Regwrite_2_regs,
    output JALFlush_2_IF,
    output [31:0] JalAddr_2_IF,
    output [31:0] wb_data,
    output [4:0] wb_addr
);

wire [31:0] wb2_data;
assign wb2_data = (MeMtoReg_from_MEM_WB)? Data_from_MEM_WB:Res_from_MEM_WB;
// if memtoreg is ture, dcache give data, else alu
assign Regwrite_2_regs = RegWrite_from_MEM_WB & (~overflow_from_MEM_WB);

assign wb_data = (JALFlush_from_MEM_WB)? pc8_from_MEM_WB:wb2_data;
assign wb_addr = (JALFlush_from_MEM_WB)? 5'd31:rd_from_MEM_WB;

assign JALFlush_2_IF =JALFlush_from_MEM_WB;
assign JalAddr_2_IF =JalAddr_from_MEM_WB;
endmodule